A commonly used method for forming metal lines and vias is known as “damascene.” Generally, this method involves forming an opening in a dielectric layer, which separates the vertically spaced metallization layers. The opening is typically formed using conventional lithographic and etching techniques. After the formation, the opening is filled with copper or copper alloys to form a via or a trench. Excess metal material on the surface of the dielectric layer is then removed by chemical mechanical polish (CMP). The remaining copper or copper alloy forms vias and/or metal lines.
Copper has replaced aluminum because of its lower resistivity. However, copper still suffers from electro-migration (EM) and stress-migration (SM) reliability issues as geometries continue to shrink and current densities increase.
FIG. 1 illustrates a cross-sectional view of an intermediate stage in the formation of a conventional interconnect structure. Copper line 4 is formed in low-k dielectric layer 2. Etch stop layer (ESL) 6 is formed on the top surface of copper line 4 and low-k dielectric layer 2. The degradation in RC delay is a shortcoming of the structure shown in FIG. 1. ESL 6 typically has a higher dielectric constant (k value) than low-k dielectric layer 2. As a result, the parasitic capacitances between the metal lines are increased, which results in the increase in RC delay.
FIG. 2 illustrates an improved interconnect structure, wherein metal cap 8 is formed on copper line 4. Metal cap 8 is typically formed of materials suffering less from electro-migration and stress-migration, for example, CoWP, tantalum, titanium, tungsten, and combinations thereof. This layer improves the reliability of the interconnect structure by reducing copper surface migration. It has been found that under stressed conditions, the mean time to failure (MTTF) of the interconnect structures with metal caps may be ten times greater than that of the interconnect structure shown in FIG. 1. With metal cap 8, the stress-induced void formation is significantly reduced. Additionally, parasitic capacitances are also reduced.
In addition to the characteristics discussed in the preceding paragraphs, the structures shown in FIGS. 1 and 2 suffer from other drawbacks. Copper line 4 and metal cap 8 are typically vulnerable to oxygen and/or chemical attacks, wherein oxygen and chemicals are introduced in the subsequent formation of the overlying low-k dielectric layers, etch stop layers, and the like. Additionally, for the structure shown in FIG. 2, the materials in metal cap 8 may adversely diffuse into the underlying copper line 4, causing an increase in the resistivity of copper line 4. Such an increase becomes a severe problem for future generations of integrated circuit, as the dimensions of the integrated circuits become increasingly smaller. Therefore, new structures and formation methods that overcome the deficiencies of the prior art are needed.